My question is about data validity and timeliness with PCI bus master
transactions.
I have a bus master PCI device. The kernel mode driver programs the DMA
controller on the bus master device to transfer data from the deviceâ??s memory
to the hostâ??s system memory. When the transfer is complete (the deviceâ??s
internal DMA FIFOs empty), the device generates a PCI interrupt to notify the
host. At this point, the ISR schedules a DPC, which performs some handling
of the completed transfer and possibly invalidates the cache for that system
memory region. I would like to know at what point a PCI bus master driver
can expect, with 100% certainty, the transferred data to be in system memory.
Is it ridiculous to imagine that the ISR/DPC processing could happen before
the host PCI bridge can shuffle all of the data into system memory? Am I
being paranoid?
I would like someone who has intimate knowledge of this process to either
ease my concerns, or give me a little direction.
Thank you,
Lou Rohan